The present invention relates to a magnetic domain memory system and more particularly, to a novel magnetic domain memory unit and a memory system of the kind employing a plurality of such units.
A major-minor memory loop chip composed of magnetic domain memory elements is shown in FIG. 1 of U.S. Pat. No. 3,618,054 (Reference 1). This chip construction was proposed to achieve a high access speed without sacrificing a memory density. Throughout the following description, in order to avoid ambiguity in terminology, the term "a magnetic momory unit" or simply "a unit" will be used to represent an arrangement comprising a sheet of magnetic material on which is formed a combination of one major loop having input and output sections and a plurality of minor loops for holding and moving magnetic domains. In order to realize a magnetic domain memory system with a required memory capacity, a large number of such units must be used.
A memory system construction in which such units are arranged in rows and columns, is disclosed in an article by Hsu Chang Bubble Domain Memory Chips IEEE TRANSACTIONS ON MAGNETICS, VOL. MAG-8, No. 3 Pages 564 to 569, especially Pages 564 to 565 (FIG. 2), September issue, 1972 (Reference 2). In this memory system construction, when a gate current is fed to a WRITE-gate conductor in response to a write-in command, magnetic domains enter into the major loop of the unit located in the selected column as well as those of the units in the unselected columns. Therefore, after the write-in operation for the selected unit has been completed, the unwanted magnetic domains thus present in the major loops of the unselected units must be erased by feeding a gate current to an ERASE-gate conductor. As a result, the write-in period is fairly long. If a request for read-out should occur while the unwanted domains are being erased, the immediate read-out operation is impossible. Since the memory system construction employing the conventional memory units has the above-mentioned disadvantage, has been desired such that a novel chip construction has been desired such that which prevents the entering of domains into the major loops of unselected units during the write-in operation
If it is assumed that the memory capacity of a unit, that is, the product of the number of bits in each minor loop and the number of minor loops is equal to B bits, the average access time required for reading out arbitrary information in a minor loop of the magnetic domain memory unit is approximately proportional to .sqroot.B. For this reason, in order to reduce the average access time, the value of B must be made small. However, this results in an increased number of the units in the magnetic memory system. With regard to the magnetic domain memory system of such construction the units that are arranged in rows and columns as disclosed in Reference 2, if the number of rows and that of columns in the row-column arrangement are chosen so as not to extremely differ from each other, the numbers of TRANSFER-gate driver circuits, ERASE-gate driver circuits, WRITE-gate driver circuits and READ-amplifiers as required are approximately proportional to the square root of the total number of the units. In this case, the number of simultaneously operating units is equal to that of the rows in the row-column arrangement.
If the memory system having the above-described construction is so designed as to operate intentionally and simultaneously the units equal in number to the number of rows in the row-column arrangement to meet the required data transfer rate, there exists no problem with respect to the system construction. However, in an extreme case, if only the data rate satisfied by the operation of only one unit is required, it is not economical to practically provide the READ-amplifiers equal in number to the rows in the row-column arrangement. On the other hand, if the number of the rows in the arrangement is determined so as to match the required data transfer rate, the number of the TRANSFER-gate driver circuits is increased, although the number of the READ- amplifiers can be minimized. Therefore, the development and the realization of a magnetic domain memory unit as well as a magnetic domain memory system employing such units and having the system construction free from the above-mentioned disadvantages have been desired.